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HD74CDC2509B
3.3-V Phase-lock Loop Clock Driver
REJ03D0825-0900 (Previous: ADE-205-218G) Rev.9.00 Apr 07, 2006
Description
The HD74CDC2509B is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The HD74CDC2509B operates at 3.3 V VCC and is designed to drive up to five clock loads per output. One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of the input clock. Output signal duty cycles are adjusted to 50 percent independent of the duty cycle at the input clock. Each bank of outputs can be enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the HD74CDC2509B does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, HD74CDC2509B requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground.
Features
* * * * * * Meets "PC SDRAM registered DIMM design support document, Rev. 1.2" Phase-lock loop clock distribution for synchronous DRAM applications External feedback (FBIN) pin is used to synchronize the outputs to the clock input No external RC network required Support spread spectrum clock (SSC) synthesizers Ordering Information
Part Name HD74CDC2509BTEL Package Type TSSOP-24 pin Package Code (Previous code) PTSP0024JB-A (TTP-24DBV) T Package Abbreviation Taping Abbreviation (Quantity) EL (1,000 pcs / Reel)
*Only by a change of a suffix (A to B) for standardization, there isn't any change of the product.
Function Table
1G X L L H H H: L: X: High level Low level Immaterial Inputs 2G X L H L H CLK L H H H H 1Y (0:4) L L L H H Outputs 2Y (0:3) L L H L H FBOUT L H H H H
Rev.9.00 Apr 07, 2006 page 1 of 7
HD74CDC2509B
Pin Arrangement
AGND 1
24 CLK 23 AVCC 22 VCC 21 2Y0 20 2Y1 19 GND 18 GND 17 2Y2 16 2Y3 15 VCC
14 2G 13 FBIN
VCC
2
1Y0 3 1Y1 4 1Y2 5 GND GND
6 7
1Y3 8 1Y4
9
VCC 10
1G 11 FBOUT 12
(Top view)
Absolute Maximum Ratings
Item Supply voltage Input voltage *1 Output voltage *1, 2 Input clamp current Output clamp current Continuous output current Supply current Maximum power dissipation *3 at Ta = 55C (in still air) Storage temperature Notes: Symbol VCC VI VO IIK IOK IO ICC or IGND PT Tstg Ratings -0.5 to 4.6 -0.5 to 6.5 -0.5 to VCC +0.5 -50 50 50 100 0.7 -65 to +150 Unit V V V mA mA mA mA W C Conditions
VI < 0 VO < 0 or VO > VCC VO = 0 to VCC
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils.
Rev.9.00 Apr 07, 2006 page 2 of 7
HD74CDC2509B
Recommended Operating Conditions
Item Supply voltage Input voltage Symbol VCC VIH VIL VI IOH IOL Ta Min 3.0 2.0 -- 0 -- -- 0 Typ -- -- -- -- -- -- -- Max 3.6 -- 0.8 VCC -12 12 85 Unit V V Conditions
Output current Operating temperature
mA C
Note: Unused inputs must be held high or low to prevent them from floating.
Logic Diagram
1G
11 3 4 5 8 9
1Y0 1Y1 1Y2 1Y3 1Y4
2G
14 21 20 17
2Y0 2Y1 2Y2 2Y3 FBOUT
CLK FBIN AVCC
24 16
PLL
13 12
23
Rev.9.00 Apr 07, 2006 page 3 of 7
HD74CDC2509B
Pin Function
Pin name CLK No. 24 I Type Description Clock input. CLK provides the clock signal to be distributed by the HD74CDC2509B clock driver. CLK is used to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to its reference signal. Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is nominally zero phase error between CLK and FBIN. Output bank enable. 1G is the output enable for outputs 1Y(0:4). When 1G is low, outputs 1Y(0:4)are disabled to a logic-low state. When 1G is high, all outputs 1Y(0:4) are enabled and switch at the same frequency as CLK. Output bank enable. 2G is the output enable for outputs 2Y(0:3). When 2G is low, outputs 2Y(0:3)are disabled to a logic low state. When 2G is high, all outputs 2Y(0:3) are enabled and switch at the same frequency as CLK. Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0:4) is enabled via the 1G input. These outputs can be disabled to a logic low state by deasserting the 1G control input. Clock outputs. These outputs provide low-skew copies of CLK. Output bank 2Y(0:3) is enabled via the 2G input. These outputs can be disabled to a logic low state by deasserting the 2G control input. Analog power supply. AVCC provides the power reference for the analog circuitry. In addition, AVCC can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs. Analog ground. AGND provides the ground reference for the analog circuitry. Power supply Ground
FBIN
13
I
1G
11
I
2G
14
I
FBOUT
12
O
1Y(0:4)
3, 4, 5, 8, 9 O
2Y(0:3)
16, 17, 20, 21 23
O
AVCC
Power
AGND VCC GND
1 Ground 2, 10, 15, 22 Power 6, 7, 18,19 Ground
Electrical Characteristics
Item Input clamp voltage Output voltage Symbol VIK VOH Min -- VCC-0.2 2.1 2.4 -- -- -- -- -- -- Typ *1 -- -- -- -- -- -- -- -- -- -- Max -1.2 -- -- -- 0.2 0.8 0.55 5 10 500 Unit V V Test Conditions VCC = 3 V, II = -18 mA VCC = Min to Max, IOH = -100 A VCC = 3 V, IOH = -12 mA VCC = 3 V, IOH = -6 mA VCC = Min to Max, IOL = 100 A VCC = 3 V, IOL = 12 mA VCC = 3 V, IOL = 6 mA VCC = 3.6 V, VIN = VCC or GND AVCC = GND, VCC = 3.6 V, VI = VCC or GND, IO = 0 AVCC = GND, VCC = 3.3 to 3.6 V One input at VCC-0.6 V, Other inputs at VCC or GND VCC = 3.3 V, VI = VCC or GND VCC = 3.3 V, VO = VCC or GND
VOL
Input current Quiescent supply current
IIN ICC ICC
A A A
Input capacitance Output capacitance Note:
CIN CO
-- --
4 6
-- --
pF pF
1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.
Rev.9.00 Apr 07, 2006 page 4 of 7
HD74CDC2509B
Switching Characteristics
(CL = 30 pF, Ta = 0 to 85C)
Item Phase error time Symbol tpe Min VCC = 3.3 V0.3 V Typ Max -- 150 Unit ps From (Input) To (Output) 66 MHz < CLKIN 100 MHz Any Y or FBOUT, F (clkin = 100 MHz) F (clkin = 100 MHz) F (clkin = 100 MHz) FBIN
-150
Between output pins skew *1
tsk (O)
--
--
200
ps
Any Y or FBOUT
Cycle to cycle jitter Duty cycle Output rise / fall time tTLH tTHL Analog power supply rejection (DC to 10 MHz) Notes: Vapsr
*2
-100 45 5.0 5.0 100
-- -- -- -- --
100 55 1.0 1.0 --
ps % volts/ns
Any Y or FBOUT Any Y or FBOUT Any Y or FBOUT Any Y or FBOUT AVCC
mVP-P
The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed. 1. The tsk(O) specification is only valid for equal loading of all outputs. 2. This parameter is characterized but not tested.
Timing Requirements
Item Input clock frequency Input clock duty cycle Stabilization time *1 Note: Symbol fclock Min 50 40 -- Max 125 60 1 Unit MHz % ms Test Conditions
After power up
1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. In order for phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay and skew parameters given in the switching characteristics table are not applicable.
Test Circuit
From output under test
*1
C L = 30 pF
500
Note:
1. CL includes probe and jig capacitance.
Rev.9.00 Apr 07, 2006 page 5 of 7
HD74CDC2509B Waveforms - 1
3V
Input
50% VCC
50% VCC 0V
Output (= FBOUT)
2V
50% VCC 0.4 V
2V 0.4 V tTHL
VOH VOL
tTLH
Notes:
1. All input pulses are supplied by generators having the following characteristics: PRR 100 MHz, ZO = 50 , tr = 1.2 ns, tf = 1.2 ns. 2. The outputs are measured one at a time with one transition per measurement.
Waveforms - 2
CLKIN
t phase error
FBIN
FBOUT
t sk (o)
Any Y
Any Y
t sk (o)
Any Y
Rev.9.00 Apr 07, 2006 page 6 of 7
HD74CDC2509B
Package Dimensions
JEITA Package Code P-TSSOP24-4.4x7.8-0.65 RENESAS Code PTSP0024JB-A Previous Code TTP-24DBV MASS[Typ.] 0.08g
*1
D
F 13
24
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
HE
E
*2
Index mark
Terminal cross section ( Ni/Pd/Au plating )
1 12
e
*3
c
Reference Dimension in Millimeters Symbol
Z
bp
x
M
L1
A1
y
L
Detail F
D E A2 A1 A bp b1 c c1 HE e x y Z L L1
Min Nom Max 7.80 8.10 4.40
0.03 0.07 0.10 1.10 0.15 0.20 0.25 0.10 0.15 0.20 0 8 6.20 6.40 6.60 0.65 0.13 0.10 0.65 0.4 0.5 0.6 1.0
Rev.9.00 Apr 07, 2006 page 7 of 7
A
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